Presentation
After having studied the basic combinational and sequential functions of digital circuits at the time of module ISP304, we propose the module ISP403 to you to analyze and understand how the assembly of these functions makes it possible to build a complex processing circuit.
The general architecture model of a digital processing circuit will be presented and illustrated through several examples. Then, the architecture of an elementary processor associated to a memory bloc containing the program will be studied. This elementary processor will be designed, using the suitable CAD tools, and implemented on an FPGA-based development board.
Prerequisites
Module ISP304 : Digital Design
Objectives
Understand the hardware architectures of the digital processing systems
Learn how to move from the algorithm to the architecture
Understand the hardware architecture of an elementary processor
Become familiar with CAD tools and development boards in Digital Design
Duration:
10h30
Content
C1: Application-specific processors
presentation of the basic architecture model of the digital processing systems
illustration through few examples
C2/C3: General-purpose processors
architectures of the general-purpose processors
advanced architectural concepts (pipeline, VLIW, superscalar, cache,...)
programming Model
application-domain specific processors (ASIPs)
presentation of the elementary processor to be designed at the time of the BE1 and BE2
BE1: Design of an elementary processor - 1st part
design of the control unit
validation by simulation
BE2: Design of an elementary processor - 2nd part
integration of all the units constituting the processor
validation using test programs
implementation on an FPGA-based development board
a report must be handed over at the end of the BE
Organization
Examination
In addition to the final exam, the handed report of both BE will be useful for the note of the continuous assessment
Scheduled activities
- C1 (1h30) Cours 1
- C2 (1h30) C2
- C3 (1h30)
- BE1 (3h) BE1
- BE2 (3h) BE2
Team
|
